Due to advancements in processing technology, complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the design is often structured in a modular manner. The designer describes a module in terms of the behavior of a system, the behavior describing the generation and propagation of signals through combinatorial modules from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher level modules.
An HDL design can be synthesized to create a logical network list (netlist), which can be implemented as an IC. Prior to implementation, the HDL design can be simulated to determine whether the design will function as required. Wasted manufacturing costs due to faulty design may thereby be avoided. Numerous tools are available for simulating circuit designs including, for example, high-level modeling systems (HLMS) and HDL simulators.
Two popular HDL languages are VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language) and Verilog. In VHDL, processes, as specifically called out in a VHDL design description, are automatically executed by a simulator while procedures in the VHDL design description are executed when called by a process. Verilog provides initial/always blocks, as well as tasks, for use in a design description. Initial and always blocks are automatically executed, and tasks are executed when called by an initial/always block. For ease of explanation and brevity, VHDL processes and procedures as well as Verilog initial/always blocks and tasks are generically referred to as processes and procedures herein.
An HDL simulator generally includes an HDL language compiler and a simulation kernel. The compiler converts input HDL files into code that is executable by a simulation kernel. In generating the executable code, the compiler maps HDL constructs into the language constructs of a target language compatible with the simulation kernel. The target language may be a general programming language, such as C/assembly, or some other proprietary language. Every process statement in an HDL design is compiled into a function in the target language. In addition, every HDL procedure is also compiled into a unique function in the target language. As used herein, a compiled process or procedure is simply referred to as the process or procedure. When simulation begins, the simulation kernel reads in the executable code generated by the compiler and executes the code according to the HDL language rules. In particular, a simulation kernel generally executes compiled processes in a loop.
Similar to the manner in which an operating system kernel schedules program execution in a computer system, functions corresponding to active processes are scheduled according to a scheduling algorithm, such as those defined by the HDL standards IEEE-1076 and IEEE-1364. The processes are executed by the simulation kernel to simulate concurrent execution of the processes in hardware over a modeled period of time. After a function has been executed, the kernel executes the other functions until all processes have been simulated for the modeled time period. When all processes have been executed, the kernel reschedules and executes active processes to model the HDL specification for the next time period. In this manner, processes may be iteratively simulated in a loop to model concurrent execution in hardware.
In an HDL simulator, procedures containing wait statements or event control pose a modeling challenge. Similar to a process, a procedure may be suspended at a wait statement or event control contained in the procedure. However, unlike a process statement, a procedure may not be statically elaborated with a reserved portion of memory. Rather, the memory for an instance of a procedure may be reallocated when the procedure completes. This presents various complexities in the implementation of an HDL simulator. For example, declarations inside a procedure may need to be preserved when that procedure is suspended due to a wait statement. This is required because common programming languages such as C/C++ do not provide a way to save the stack of a called function and then use it to resume the function in the same state as it was prior to the wait. In order to address these complexities, a lot of bookkeeping code is required, which may affect the speed of simulation. All or some of the bookkeeping code may be generated by the compiler, which increases complexity of the compiler itself. For the sake of simplicity, wait statements and event control are generically referred to as wait statements herein.
The disclosed embodiments may address one or more of the above issues.